1. Field of the Invention
The present invention relates to testing of high speed circuits with minimized mechanical damage to the circuit's test pads. The invention more particularly concerns high throughput and high bandwidth testing of such high speed circuits by use of opto-electronic devices.
2. Description of Related Art
Integrated circuits, (ICs), and monolithic microwave or millimeter wave integrated circuits (MMICs) are manufactured with large numbers of identical circuits on a single wafer. Individual circuits are ultimately separately cut from the wafer for use as chips. It is desirable to test each circuit individually to determine whether or not it functions as intended before separating it from the wafer. Additional testing of separated circuits may be desired at various stages of the assembly of the circuit in the finished apparatus. Still further testing may be accomplished after mounting a circuit in a hybrid package, after placing a circuit in a multi-chip module, after disassembly of a multi-chip module to identify inoperable circuits, and even after the circuit's final packaging operation.
Conventional electromechanical testing employs either individual probe arms or a single probe card that is provided with a multitude (two or more) of small tungsten blades or needles that are mechanically and electrically connected to the circuit-under-test and act as test probe contacts. Electrical leads on the probe armor card extend from the contacts to the outer edge of the board for connecting the probe card to test circuitry. In use, the blades or needles are moved into engagement with the pads of an integrated circuit. The motion has to be such that there is a slight scrubbing action that is required for breaking through oxidation coating that often covers an aluminum pad. Thus, blades or needles are frequently positioned at an angle so that they will effectively slide along or scrub a surface of the pad to break the oxide coating. This provides an electrical connection so that signals can be read to determine integrity of the circuit on the chip.
Ends of the test needles or blades must all fall in the same plane in order to assure that each one makes electrical contact with a pad of the integrated circuit. This is accomplished by bending the blades or needles after they are mounted on the probe card, which is laborious, time consuming and expensive. Even after such adjustment, the blades or needles tend to creep back toward their original position so that their adjusted locations are lost. This loss of adjustment also comes about from the pressure of the needles against the chips, aggravated by the scrubbing action used to assure penetration of an oxide coating. As a result, constant maintenance is necessary or the probe cards will not perform their intended function. Even when in proper adjustment the needles cannot compensate for significant differences in the heights of the contact pads on the integrated circuit chips being tested. The close spacing necessary for testing some chips cannot be achieved with conventional needle contacts. The needles may also apply excessive force against the chip so as to damage the chip or its contact pads. This problem is greatly magnified by the fact that a single chip may require testing at different stages in its assembly into a finished module. In fact, some specifications will limit the number of times that a single chip can be tested in order to avoid excessive chip damage caused by the testing operation itself.
Improved testing arrangements are disclosed in a co-pending application Ser. No. 07/606,676, filed Oct. 31, 1991, now U.S. Pat. No. 5,148,103, by John Pasiecznik, Jr. for Method and Apparatus for Testing Integrated Circuits, and in a co-pending application Ser. No. 07/752,422, filed Aug. 30, 1991 by Blake F. Woith and William R. Crumly for Rigid Flex Circuits With Raised Features as IC Test Probes, now U.S. Pat. No. 5,264,787. Both of these applications are assigned to the same assignee as that of this application, and both are incorporated herein by reference as though fully set forth.
In the above-identified application of John Pasiecznik, Jr. a flexible membrane is provided with raised features on one side which connect through conductive circuit traces to a probe card that is in turn connected to the test circuitry. During use of the membrane probe for testing, probe pressure deflects the membrane to ensure that raised contacts formed on the membrane are pressed against the pads of an integrated circuit to provide an electrical connection. Electrical traces are also formed on the membrane to electrically connect the raised probe test contacts to test circuitry. The membrane probes of the above-identified co-pending applications may not operate satisfactorily at frequencies above about 20 GHz, at least in part because of the length and mutual proximity of conductive traces on the membrane required to electrically connect the membrane probe test contacts with external test signal generators. Accordingly, high frequency test signal generators operating at frequencies beyond 20 GHz cannot be employed when testing with a prior membrane probe. Moreover, there may be required such a large number of impedance-matched metallic conductive traces on the membrane itself as to significantly stiffen the membrane, which thus is unable to utilize or to obtain maximum advantage from the inherent membrane flexibility.
Membrane probes of the above-identified applications may encounter difficulty in optimizing membrane flexibility to obtain positive electrical contacts while avoiding drooping of the membrane center.
In the past, high frequency test signal generators and measurement instruments have required special types of high bandwidth test connections to a circuit under test. Some of such signal generators and measurement circuits have been mounted directly on the surface of a wafer bearing chips to be tested, but this consumes valuable surface area of the wafer and chip, and thus degrades efficiency and cost-effectiveness of production. Alternatively, extremely delicate, high frequency test equipment has been mechanically and electrically connected to the probe pads of a circuit using numerous individually-positioned microwave probe arms, rigid or semi-rigid microwave transmission lines, and other specialized connectors. Such connector mounting, fixturing, and positioning is highly laborious and greatly impedes production throughput.
Prior optical arrangements for testing high frequency circuits are unable to satisfactorily accomplish ultra high bandwidth excitation of the device under test or absolute voltage measurements at specified circuit nodes at high device throughput rates. Some of the prior test arrangements for electro-optic substrate probing have required the circuit to be biased up, driven and loaded with conventional test fixtures, such as those involving sharp needles or blades, which tend to damage the circuit's test pads, or wire bonds. These requirements have limited the prior test arrangements to very low-throughput applications.
Electro-optic substrate probing, such as shown by U.S. Pat. No. 4,681,449 to D. M. Bloom and B. H. Kolner, entitled High Speed Testing of Electronic Circuits by Electro-Optic Sampling, does not, by itself, accomplish high throughput, ultra high bandwidth testing. Furthermore, by itself, it fails to accomplish ultra high bandwidth optical excitation of the circuit-under-test; and it does not perform absolute voltage measurements at specified circuit nodes. Moreover, utilizing the arrangement described in Bloom and Kolner's patent, and the arrangements described by K. Weingarten, M. Rodwell, and D. Bloom in an article entitled "Picosecond Optical Sampling of Gallium Arsenide GaAs Integrated Circuits", in the IEEE Journal of Quantum Mechanics, Volume 24, No. 2, Pages 198-220, February 1988, requires conventional test fixtures, such as rigid blades or needles which may damage the circuit's test pads or wire bonds. Another disadvantage of prior-art electro-optic substrate probing is that wafer thickness variations can result in widely varying optical reflectivities from micro-strip ground planes due to Fabry-Perot or optical standing wave interference effects in a thinned wafer, especially for circuit locales having no passivation layers on their top surfaces. This problem is especially troublesome in topside electro-optic substrate probing of microstrip circuit geometries, which employs the optical reflectivity of certain planes in the substrate, particularly when sampling pulse lengths are comparable to or longer than the thicknesses of the thinned wafers (50-100 micrometers typical).
In an article entitled "Picosecond Backside Optical Detection of Internal Signals in Flip-Chip Mounted Silicon VLSI Circuits", H. K. Heinrich, N. Pakdaman, J. L. Prince, D. S. Kent, and L. M. Cropp published in Microelectronic Engineering, volume 16, pages 313-324, Elsevier, 1992, there is described a method for interferometrically sensing spot-to-spot variations in free charge densities in an integrated circuit fabricated on a semiconductor material. From these charge density variations, high-bandwidth currents and voltage waveforms can be inferred. This technique, like that in Bloom and Kolner's patent, requires conventional test fixtures which will slow down the test through put and which may damage the circuit.
In an article entitled "Novel Approach To Miniature Conductive Sampling Of Microwave Circuits", S. L. Huang, L. P. Golob, C. H. Lee and H. A. Hung, published in the JFD2 Conference on Laser and Electro-Optics, Anaheim, Calif. May 10-15, 1992, there is described on-wafer photoconductive measurements of the S-parameters of a 60 GHz monolithic microwave integrated circuit (MMIC) low noise amplifier by integrating six very closely spaced photoconductive gaps at the input and output of a 60 GHz MMIC chip. This arrangement requires fabrication of photoconductive gaps directly on the chip itself, thereby adding complexity to chip design, decreasing chip yield and complicating its fabrication. Other workers have described a method to electro-optically measure the S-parameters of an electrical device by using standard, destructive electrical connections to launch the electrical output of this device into a separate 50% transmission line fabricated on a rigid piece of electro-optic material. The connection requirements of this arrangement prohibit its use in high-throughput test applications.
Accordingly, it is an object of the present invention to provide for the testing of circuits, including very high frequency circuit devices, by apparatus and methods that eliminate or avoid the above-mentioned problems.